1. Field of the Invention
This invention relates to a driving apparatus of a display panel having capacitive light emitting devices arranged in matrix form.
2. Description of the Related Art
A display apparatus having a plasma display panel mounted thereto is now commercially available as the display panel described above (for example, Japanese Patent Kokai No. 2000-155557 (Patent Reference 1)).
FIG. 1 schematically shows the construction of such a display apparatus.
Referring to FIG. 1, row electrodes Y1 to Yn and row electrodes X1 to Xn are shown to be formed in a PDP1 as the plasma display panel, whereby each pair of X and Y constitute a row electrode pair corresponding to each row (first to nth rows) of one screen. Column electrodes D1 to Dm respectively constituting column electrodes corresponding to columns (first to nth columns) of one screen are further formed in such a way as to intersect these row electrode pairs and to sandwich a dielectric layer and discharge spaces, not shown in the drawing. In this case, each discharge cell as a capacitive light emitting device is formed at each point of intersection between each row electrode pair and each column electrode. An address driver 2 converts pixel data of each pixel based on an image signal to a pixel data pulse having a voltage value corresponding to a logic level of the data and applies this pixel data pulse to the column electrodes D1 to Dm for each row. An X row electrode driver 3 generates a reset pulse for initializing a residual wall charge amount of each discharge cell and a sustain discharge pulse for keeping a discharge light emission state of the discharge cell set to an ON mode which will be explained later, and applies these pulses to the row electrodes X1 to Xn. A Y rowelectrode driver 4 generates a reset pulse for initializing the residual wall charge amount of each discharge cell and a sustain discharge pulse for keeping the discharge light emission state of the discharge cell in the same way as the X row electrode driver 3, and applies these pulses to the row electrodes Y1 to Yn. The Y row electrode driver 4 further generates a priming pulse for re-forming charge particles inside the discharge cell and a scan pulse SP for forming a charge amount corresponding to the pixel data pulse for each discharge cell and setting each discharge cell to either the ON mode or the OFF mode, and applies these pulses to the row electrodes Y1 to Yn.
FIG. 2 shows an internal construction of the X row electrode driver 3 and the Y row electrode driver 4. Incidentally, an electrode Xj in FIG. 2 represents an electrode of a jth row among the electrodes X1 to Xn, and an electrode Yj represents an electrode of the jth row among the electrodes Y1 to Yn.
The X row electrode driver 3 has two power sources B101 and B102. The power source B101 outputs a voltage Vs1 (for example, 170 V) and the power source B102 outputs a voltage Vr1 (for example, 190V). A positive terminal of the power source B101 is connected to a connection line 111 of the electrode Xj through a switching device S103 and its negative terminal is grounded. A switching device S104 is interposed between the connection line 111 and the ground. A series circuit including a switching device S101, a diode D101 and a coil L101 and a series circuit including a coil L102, a diode D102 and a switching device S102 are connected to the ground through a capacitor C101 in common. The diode D101 has its anode on the side of the capacitor C101 and the diode D102 has its cathode on the side of the capacitor C101. A positive terminal of the power source B102 is connected to the connection line 111 through a switching device S108 and a resistor R101 and its negative terminal is connected to the ground. The Y row electrode driver 4 has four power sources B103 to B106. The power source B103 outputs the voltage Vs1 (for example, 170 V). The power source B104 outputs the voltage Vr1 (for example 190 V). The power source B105 outputs a voltage Voff (for example, 140 V) and the power source B106 outputs a voltage Vh (for example, 160 V, Vh>Voff). A positive terminal of the power source B103 is connected to a connection line 112 to a switching device S115 through a switching device S113 and its negative terminal is grounded. A switching device S114 is interposed between the connection line 112 and the ground. A series circuit including a switching device S111, a diode D103 and a coil L104 and a series circuit including a coil L104, a diode D104 and a switching device S112 are connected to the ground through a capacitor C102 in common. The diode D103 has its anode on the side of the capacitor C102 and the diode D104 has its cathode on the side of the capacitor C102. The connection line 112 is connected to a connection line 113 of a positive terminal of the power source B106 through a switching device S115. A positive terminal of the power source B104 is connected to the ground and its negative terminal is connected to the connection line 113 through a switching device S116 and a resistor R102. A positive terminal of the power source B105 is connected to the connection line 113 through a switching device S117 and its negative terminal is grounded. The connection line 113 is connected to a connection line 114 to the electrode Yj through a switching device S121. A negative terminal of the power source B106 is connected to the connection line 114 through a switching device S122. A diode D105 is connected between the connection lines 113 and 114 and a series circuit of a switching device S123 and a diode D106 is connected to the diode D105. The diode D105 has its anode on the side of the connection line 114 and the diode D106 has its cathode on the side of the connection line 114.
Here, a control circuit, not shown in the drawing, controls ON/OFF switching of the switching devices S101 to S104, S111 to S117 and S121 to S123.
Incidentally, the power source B103, the switching devices S111 to S115, the coils L103 and L104, the diodes D103 and D104 and the capacitor C102 inside the Y row electrode driver 4 constitute a sustain driver part. The power source B104, the resistor R102 and the switching device S116 constitute a reset driver part. The remaining power sources B105 and B106, switching devices S113, S117, S121 and S122 and diodes D105 and D106 constitute a scan driver part.
Next, the operation in the construction described above will be explained with reference to a timing chart of FIG. 3.
As shown in FIG. 3, driving of the PDP 1 is conducted dividedly in a reset period, an address period and a sustain period.
First of all, in the reset period, the switching device S123 of the Y row electrode driver 4 turns ON. The switching device S123 remains ON in the reset period and the sustain period. At the same time, the switching device S108 of the X row electrode driver 3 turns ON and the switching device S116 of the Y row electrode driver 4 turns ON. Other switching devices remain OFF. When the switching device S108 is turned ON, a current flows from the positive terminal of the power source B102 to the electrode Xj through the switching device S108 and the resistor R101. When the switching device S116 is turned ON, a current flows from the electrode Yj into the negative terminal of the power source B104 through the diode D106, the resistor R102 and the switching device S116. In this case, the potential on the electrode Xj gradually rises due to the time constant of the load capacitance Co and the resistor R101 of the PDP 1, generating the reset pulse RPx as shown in FIG. 3. On the other hand, the potential of the electrode Yj gradually lowers due to the time constant of the load capacitance C0 and the resistor R102, generating the reset pulse RPy as shown in FIG. 3. The reset pulse RPx is simultaneously applied to all electrodes X1 to Xn and the reset pulse RPy is simultaneously applied to all electrodes Y1 to Yn. As these reset pulses RPx and RPy are simultaneously applied, reset discharge is induced inside all discharge cells of the PDP 1. After the finish of this discharge, wall charge of a predetermined amount is uniformly generated in the dielectric layer of all discharge cells. Such reset discharge initializes all discharge cells to the ON mode. After the levels of the reset pulses RPx and RPy get into saturation, the switching devices S108 and S116 turn OFF before the termination of the reset period. At this point, the switching devices S104, S114 and S115 are turned ON and both electrodes Xj and Yj are grounded. In consequence, the reset pulses RPx and RPy disappear.
Next, in the address period, the switching devices S114 and S115 turn OFF, the switching device S123 turns OFF, the switching device S117 turns ON and at the same time, the switching device S122 turns ON. As the switching device S117 is turned ON, the power source B105 and the power source B106 are connected in series, and a negative potential representing the difference between the voltages Vh and Voff appears at the negative terminal of the power source B106 and is applied to the electrode Yj. In this address period, the address driver 2 converts the pixel data for each pixel based on the image signal to pixel data pulses DP1 to DPn having a voltage value corresponding to the logic level of the image data and serially applies these data pulses to the column electrodes D1 to Dm. As shown in FIG. 3, the image data pulses DPj and DPj+1 are applied to the electrodes Yj and Yj+1. In the mean time, the Y row electrode driver 4 serially applies the priming pulse PP of the positive voltage to the row electrodes Y1 to Yn, and also applies serially the scan pulse SP of the negative voltage to the row electrode Y1 to Yn in synchronism with each timing of the pixel data pulse group DP1 to DPn immediately after the application of each priming pulse PP. Explanation will be given on the electrode Yj. When generating the priming pulse PP, the switching device S121 turns ON and the switching device S122 turns OFF. The switching device S117 remains ON. In consequence, the potential Voff of the positive terminal of the power source B105 is applied as the priming pulse PP to the electrode Yj through the switching device S117 and then through the switching device S121. After the application of this priming pulse PP, the switching device S121 turns OFF while the switching device S122 turns ON in synchronism with the application of the pixel data pulse DPj from the address driver 2. In consequence, a negative potential representing the difference between the voltage Vh of the negative terminal of the power source B106 and the Voff is applied as the scan pulse SP to the electrode Yj. In synchronism with the stop of the application of the pixel data pulse DPj from the address driver 2, the switching device S121 turns ON and the switching device S122 turns OFF. The potential Voff of the positive terminal of the power source B105 is applied to the electrode Yj through the switching device S117 and then through the switching device S121. As to the electrode Yj+1, too, the priming pulse PP is thereafter applied in the same way as the electrode Yj as shown in FIG. 3 and the scan pulse SP is applied in synchronism with the application of the pixel data pulse DPj+1 from the address driver 2. Discharge develops in the discharge cells to which the pixel data pulse of the positive voltage is further applied simultaneously among the discharge cells belonging to the row electrodes to which the scan pulse SP is applied, and the wall charge is mostly lost. On the other hand, discharge does not develop in the discharge cells to which the scan pulse SP is applied but the pixel data pulse of the positive voltage is not applied, and the wall charge remains as such. In this case, the discharge cells the wall charge of which disappears are set to the OFF mode and the discharge cells the wall charge of which remains are set to the ON mode. When the address period shifts to the sustain period, the switching devices S117 and S121 turn OFF and the switching devices S114 and S115 turn ON instead. The ON state of the switching device S104 is continued.
In the sustain period, the switching device S104 of the X row electrode driver 3 is turned ON and consequently, the potential of the electrode Xj reaches the ground potential that is substantially 0 V. Next, when the switching device S104 is turned OFF and the switching device S101 is turned ON, a current resulting from the charge stored in the capacitor C1 flows into the electrode Xj through the coil L101, the diode D101 and the switching device S101 and charges the load capacitance C0 of the PDP 1. In this process, the potential of the electrode Xj gradually moves up due to the time constant of the coil L101 and the load capacitance C0 as shown in FIG. 3. Next, the switching device S101 turns OFF and the switching device S103 turns ON. In consequence, the potential Vs1 of the positive terminal of the power source B101 is applied to the electrode Xj. The switching device S103 is thereafter turned OFF, the switching device S102 is turned ON and a current resulting from the charge stored in the load capacitance C0 flows from the electrode Xj into the capacitor C101 through the coil L102, the diode D102 and then through the switching device S102. In this case, the potential of the electrode Xj gradually lowers due to the time constant of the coil L102 and the capacitor C101 as shown in FIG. 3. When the potential of the electrode Xj reaches substantially 0 V, the switching device S102 turns OFF and the switching device S104 turns ON. Due to this operation, the X row electrode driver 3 applies the sustain discharge pulse IPx of the positive voltage such as shown in FIG. 3 to the electrode Xj. At the time of turn-ON of the switching device S104 at which the sustain discharge pulse IPx disappears, the switching device S111 of the Y row electrode driver 4 turns ON while the switching device S114 turns OFF. When the switching device S114 is ON, the potential of the electrode Yj is at the ground potential that is substantially 0 V. When the switching device S114 is turned OFF and the switching device S111 is turned ON, however, a current resulting from the charge stored in the capacitor C102 flows into the electrode Yj through the coil L103, the diode D103, the switching devices S111, S115 and S113 and the diode D106, and charges the load capacitance C0 of the PDP1. In this case, the potential of the electrode Yj gradually moves up due to the time constant of the coil L103 and the load capacitance C0 as shown in FIG. 3. Next, the switching device S111 turns OFF and the switching device S113 turns ON. Consequently, the potential Vs1 of the positive terminal of the power source B103 is applied to the electrode Yj. Thereafter, the switching device S113 is turned OFF, the switching device S112 is turned ON and a current resulting from the charge stored in the load capacitor C0 flows from the electrode Yj to the capacitor C102 through diode D105, the switching device S115, the coil L104, the diode D104 and then the switching device S112. In this case, the potential of the electrode Yj gradually lowers due to the time constant of the coil L104 and the capacitor C102 as shown in FIG. 3. When the potential of the electrode Yj reaches substantially 0 V, the switching device S112 turns OFF and the switching device S114 turns ON. By this operation, the Y row electrode driver 4 applies the sustain discharge pulse IPy of the positive voltage such as shown in FIG. 3 to the electrode Yj.
As described above, the sustain discharge pulse IPx and the sustain discharge pulse IPy are alternately applied to the electrodes X1 to Xn and to the electrodes Y1 to Yn in the sustain period. Therefore, only the discharge cells the wall charge of which remains, that is, only the discharge cells set to the ON mode, repeat discharge light emission and keep the light emission state.
Incidentally, reset discharge induced so as to initialize altogether the wall charge amounts inside all discharge cells during the reset period must be relatively strong discharge. Therefore, the pulse voltage (−Vr1) of the reset pulse RPy is set to a voltage level higher than the pulse voltage of the sustain discharge pulse IPy. For this purpose, the power source B104 (voltage Vr1) for generating the voltage higher than the voltage Vs1 of the power source B103 for generating the sustain discharge pulse IPy is disposed, and results in the increase of the circuit scale. In addition, the voltage values of the power sources B103 and B104 are mutually different and the switching devices S113, S115 and S116 interposed between these power sources B103 and B104 are the semiconductor switches, so that the possibility exists that the reverse current flows between the power sources B103 and B104. Furthermore, light emission with reset discharge does not at all participate in the display image, the lowering of contrast occurs.
The invention is completed to solve the problems described above and aims at providing a driving apparatus of a display panel that can reduce the scale of the circuit.
It is another object of the invention to provide a driving apparatus of a display panel that can reduce a circuit scale while suppressing the drop of contrast.